Such an offset correction circuit is e.g. described in the published PCT patent application PCT/US90/05358. The offset correction circuit described herein forms part of a receiver receiving an input signal which is modulated on a carrier and which includes an offset correction part with a known average value. Upon reception of this offset correction part its average value is measured and subtracted from the known average value in a digital signal processor (DSP), the result of which gives an offset correction value for "subsequently received data information" of the input signal. It is however clear that such an offset correction circuit can only be implemented when the input signal includes such an offset correction part, and that this has a negative impact on the throughput capacity of a communication system which includes a receiver with such an offset correction circuit. This is all the more valid as the offset correction value is only updated upon receipt of-a new offset correction part and thus a sufficient number of offset correction parts is to be transmitted per unit of time in order to accurately keep track of offset changing in time. Furthermore, if the offset depends upon a variable parameter this parameter dependency is not considered.